A self-aligned silicide (salicide) technology is used for the metal contact of devices without any additional mask. A conventional salicide technology will be described as below with reference to FIGS. 1 to 3.
Referring to FIG. 1, a cross sectional view of a substrate 100 is demonstrated. A metal oxide semiconductor field effect transistor (MOSFET) and a shallow trench 110 are fabricated in the substrate 100. The silicon oxide material is refilled into the trench 110 for isolation. The MOSFET in the substrate has a gate structure 120, spacers 140 of the gate structure and doping regions 130 to be the source/drain region of the MOSFET. The substrate 100 is a silicon substrate and the spacers 140 are formed of silicon oxide material.
As being shown in FIG. 2, a metal layer 150 is conformally formed on the MOSFET and the substrate 100 by physical vapor deposition (PVD) process, such as sputtering. The metal layer is formed of a refractory metal and it is selected from the group of titanium (Ti) metal, platinum (Pt) metal and cobalt (Co) metal. Afterwards, the substrate 100 is performed by a two-step rapid thermal annealing (RTA) process to convert the metal layer 150 into a silicide layer 160. The metal layer 150 is reacted with silicon atoms to form the silicide layer 160. The silicide layer 160 is formed on the top surface of the gate structure 120, the doping region 130 and the substrate 100. Besides, the metal layer 150 will not react with the silicon oxide material, for example, the spacers 140 of the gate structure 120 and the trench isolation. The bridging between the gate structure 120 and the doping region 130 is eliminated without any etch-back process. After the formation of the silicide layer 160, the residual metal layer 150 on the spacer 140 and the shallow trench 110 are removed by using an etchant, which will not attack the silicide layer 160.
It is easy to manufacture the metal contacts of the active region of a device by using salicide technology. Thus, as device being scaled down to sub-quarter micron, a narrow-linewidth effect is occurred in the salicide process. Referring to FIG. 3 again, in the sub-quarter integrated circuits, the gate structure 120 has a width W2 about 0.25 micron meters and the gate structure 120 with spacer 140 has a width about 0.4 micron meters. The width W2 is too small so as, that the silicide layer 160 is hard to be formed on the gate structure 120.
According to the above discussions, a new salicide technology is needed to form a silicide layer on the narrow gate structure of a device for sub-quarter micron integrated circuit. cl SUMMARY OF THE INVENTION
A method for manufacturing a silicide layer on a substrate is disclosed in the present invention. A substrate is provided with a MOSFET and a trench. The trench is refilled with insulating material for isolation. The MOSFET has a gate, two doping regions and spacers of the gate structure.
Then, a silicon layer is anisotropically deposited on the top surface of the device and the substrate by using ion metal plasma (IMP) technology. A refractory metal is deposited on the silicon layer. After the silicon layer and the metal layer are formed, a two-step thermal annealing process, such as rapid thermal annealing (RTA) process, is performed to form a silicide layer.
The silicide layer is formed on the top surface of the device and the substrate. Specifically, the silicide layer can be formed on the spacers and the insulating material of the trench in spite that the spacers and the insulating material are formed of silicon oxide material. Since the silicon layer serves as a silicon source for the salicide process, the silicide layer can form on the silicon oxide material.
In addition to the above benefits, the present invention has several benefits. The first benefit is that the narrow-linewidth phenomenon for sub-quarter micron integrated circuits is eliminated. The second benefit is that the local interconnect is formed during the salicide process. The third benefit is that a borderless contact hole is used for sub-quarter micron integrated circuits. The fourth benefit is that the salicide process is not influenced by the doping polarity of the active region of integrated circuits. Additionally, as the formation of the silicide layer on the source/drain regions may not reduce the depth of the source/drain regions, a junction leakage in the source/drain regions could be eliminated.